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1

[IEEE 2009 IEEE Custom Integrated Circuits Conference (CICC) - San Jose, CA, USA (2009.09.13-2009.09.16)] 2009 IEEE Custom Integrated Circuits Conference - Split capacitor DAC mismatch calibration in successive approximation ADC

Chen, Yanfei, Zhu, Xiaolei, Tamura, Hirotaka, Kibune, Masaya, Tomita, Yasumoto, Hamada, Takayuki, Yoshioka, Masato, Ishikawa, Kiyoshi, Takayama, Takeshi, Ogawa, Junji, Tsukamoto, Sanroku, Kuroda, Tada

Année:

2009

Langue:

english

Fichier:

PDF, 1.11 MB

english, 2009

2

[IEEE 2010 IEEE Custom Integrated Circuits Conference -CICC 2010 - San Jose, CA, USA (2010.09.19-2010.09.22)] IEEE Custom Integrated Circuits Conference 2010 - A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2–;10 Gb/s ADC-based receivers

Tahmoureszadeh, Tina, Sarvari, Siamak, Sheikholeslami, Ali, Tamura, Hirotaka, Tomita, Yasumoto, Kibune, Masaya

Année:

2010

Langue:

english

Fichier:

PDF, 278 KB

english, 2010

3

An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”

Shivnaraine, Ravi, Jalali, Mohammad Sadegh, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Année:

2014

Langue:

english

Fichier:

PDF, 2.53 MB

english, 2014

4

[IEEE 2013 IEEE Custom Integrated Circuits Conference - CICC 2013 - San Jose, CA, USA (2013.09.22-2013.09.25)] Proceedings of the IEEE 2013 Custom Integrated Circuits Conference - An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

Jalali, Mohammad Sadegh, Shivnaraine, Ravi, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Année:

2013

Langue:

english

Fichier:

PDF, 1.63 MB

english, 2013

5

[IEEE 2014 IEEE Custom Integrated Circuits Conference - CICC 2014 - San Jose, CA, USA (2014.9.15-2014.9.17)] Proceedings of the IEEE 2014 Custom Integrated Circuits Conference - A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE

Ting, Clifford, Jalali, Mohammad Sadegh, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Année:

2014

Langue:

english

Fichier:

PDF, 745 KB

english, 2014

6

[OSA Optical Fiber Communication Conference - Los Angeles, California (2015..-..)] Optical Fiber Communication Conference - A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects

hayakawa, akinori, Kibune, Masaya, Toda, Asako, Tanaka, Shinsuke, Simoyama, Takasi, Chen, Yanfei, Akiyama, Tomoyuki, Okumura, Shigekazu, Baba, Takeshi, Akahoshi, Tomoyuki, Ueno, Seiji, Kazunori, Maruy

Année:

2015

Fichier:

PDF, 262 KB

2015

7

Photoluminescence excitation spectroscopy of GaP1−xNx alloys: conduction-band-edge formation by nitrogen incorporation

Hiroyuki Yaguchi, Seiro Miyoshi, Goshi Biwa, Masaya Kibune, Kentaro Onabe, Yasuhiro Shiraki, Ryoichi Ito

Journal:

Journal of Crystal Growth

Année:

1997

Langue:

english

Fichier:

PDF, 254 KB

english, 1997

8

[IEEE 2008 IEEE Custom Integrated Circuits Conference - CICC 2008 - San Jose, CA, USA (2008.09.21-2008.09.24)] 2008 IEEE Custom Integrated Circuits Conference - A dynamic offset control technique for comparator design in scaled CMOS technology

Xiaolei Zhu,, Yanfei Chen,, Masaya Kibune,, Yasumoto Tomita,, Takayuki Hamada,, Hirotaka Tamura,, Sanroku Tsukamoto,, Tadahiro Kuroda,

Année:

2008

Langue:

english

Fichier:

PDF, 549 KB

english, 2008

9

[IEEE 2011 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2011.02.20-2011.02.24)] 2011 IEEE International Solid-State Circuits Conference - A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS

Abiri, Behrooz, Shivnaraine, Ravi, Sheikholeslami, Ali, Tamura, Hirotaka, Kibune, Masaya

Année:

2011

Langue:

english

Fichier:

PDF, 746 KB

english, 2011

10

[IEEE 2010 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2010.02.7-2010.02.11)] 2010 IEEE International Solid-State Circuits Conference - (ISSCC) - A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

Yamaguchi, Hisakatsu, Tamura, Hirotaka, Doi, Yoshiyasu, Tomita, Yasumoto, Hamada, Takayuki, Kibune, Masaya, Ohmoto, Shuhei, Tateishi, Keita, Tyshchenko, Oleksiy, Sheikholeslami, Ali, Higuchi, Tomokazu

Année:

2010

Langue:

english

Fichier:

PDF, 922 KB

english, 2010

11

A Blind Baud-Rate ADC-Based CDR

Ting, Clifford, Liang, Joshua, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Journal:

IEEE Journal of Solid-State Circuits

Année:

2013

Langue:

english

Fichier:

PDF, 2.13 MB

english, 2013

12

[IEEE 2011 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2011.02.20-2011.02.24)] 2011 IEEE International Solid-State Circuits Conference - A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS

Abiri, Behrooz, Sheikholeslami, Ali, Tamura, Hirotaka, Kibune, Masaya

Année:

2011

Langue:

english

Fichier:

PDF, 653 KB

english, 2011

13

[IEEE 2010 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2010.02.7-2010.02.11)] 2010 IEEE International Solid-State Circuits Conference - (ISSCC) - A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS

Tyshchenko, Oleksiy, Sheikholeslami, Ali, Tamura, Hirotaka, Tomita, Yasumoto, Yamaguchi, Hisakatsu, Kibune, Masaya, Yamamoto, Takuji

Année:

2010

Langue:

english

Fichier:

PDF, 916 KB

english, 2010

14

[IEEE 2011 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2011.02.20-2011.02.24)] 2011 IEEE International Solid-State Circuits Conference - A pattern-guided adaptive equalizer in 65nm CMOS

Shahramian, Shayan, Ting, Clifford, Sheikholeslami, Ali, Tamura, Hirotaka, Kibune, Masaya

Année:

2011

Langue:

english

Fichier:

PDF, 942 KB

english, 2011

15

[IEEE 2010 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2010.06.16-2010.06.18)] 2010 Symposium on VLSI Circuits - A 5Gb/s speculative DFE for 2x blind ADC-based receivers in 65-nm CMOS

Sarvari, Siamak, Tahmoureszadeh, Tina, Sheikholeslami, Ali, Tamura, Hirotaka, Kibune, Masaya

Année:

2010

Langue:

english

Fichier:

PDF, 1022 KB

english, 2010

16

[IEEE 2014 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2014.6.10-2014.6.13)] 2014 Symposium on VLSI Circuits Digest of Technical Papers - On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs

Liang, Joshua, Jalali, Mohammad Sadegh, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Année:

2014

Langue:

english

Fichier:

PDF, 376 KB

english, 2014

17

A Reference-Less Single-Loop Half-Rate Binary CDR

Jalali, Mohammad Sadegh, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Journal:

IEEE Journal of Solid-State Circuits

Année:

2015

Langue:

english

Fichier:

PDF, 2.67 MB

english, 2015

18

[IEEE 2015 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2015.2.22-2015.2.26)] 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers - 22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI

Chen, Yanfei, Kibune, Masaya, Toda, Asako, Hayakawa, Akinori, Akiyama, Tomoyuki, Sekiguchi, Shigeaki, Ebe, Hiroji, Imaizumi, Nobuhiro, Akahoshi, Tomoyuki, Akiyama, Suguru, Tanaka, Shinsuke, Simoyama,

Année:

2015

Langue:

english

Fichier:

PDF, 726 KB

english, 2015

19

A 3x blind ADC-based CDR for a 20 dB loss channel

Jalali, Mohammad Sadegh, Ting, Clifford, Liang, Joshua, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Année:

2015

Langue:

english

Fichier:

PDF, 3.11 MB

english, 2015

20

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Liang, Joshua, Jalali, Mohammad Sadegh, Sheikholeslami, Ali, Kibune, Masaya, Tamura, Hirotaka

Journal:

IEEE Journal of Solid-State Circuits

Année:

2015

Langue:

english

Fichier:

PDF, 2.28 MB

english, 2015

21

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

CHEN, Yanfei, ZHU, Xiaolei, TAMURA, Hirotaka, KIBUNE, Masaya, TOMITA, Yasumoto, HAMADA, Takayuki, YOSHIOKA, Masato, ISHIKAWA, Kiyoshi, TAKAYAMA, Takeshi, OGAWA, Junji, TSUKAMOTO, Sanroku, KURODA, Tada

Journal:

IEICE Transactions on Electronics

Année:

2010

Langue:

english

Fichier:

PDF, 1.42 MB

english, 2010

22

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology

ZHU, Xiaolei, CHEN, Yanfei, KIBUNE, Masaya, TOMITA, Yasumoto, HAMADA, Takayuki, TAMURA, Hirotaka, TSUKAMOTO, Sanroku, KURODA, Tadahiro

Journal:

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences

Année:

2010

Langue:

english

Fichier:

PDF, 1.10 MB

english, 2010